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  • 1 - Introduction and Basics (ETH Zürich, Fall
  • 2a - Memory Refresh
  • 2b - Course Logistics
  • 3 - Computer Memory - Trends and Challenges
  • 4a - Computer Memory - Solution Ideas
  • 4b - RowHammer
  • 5 - Accelerating Genome Analysis
  • 6a - RowHammer II
  • 6b - Computation in Memory
  • 7 - Computation in Memory II
  • 8 - Computation in Memory III
  • 9a - Simulation
  • 9b - Low-Latency Memory
  • 10 - Low-Latency Memory
  • 11a - DRAM Latency PUF
  • 11b - D-RaNGe - True Random Number Generatio
  • 11c - Voltron - Reducing DRAM Energy
  • 11d - EDEN - Reducing Memory Energy in DNNs
  • 12a - EIN - Understanding DRAM Error Correction
  • 12b - SoftMC - A Flexible Memory Controller
  • 12c - CROW - Improving DRAM Perf. and Energy
  • 12d - SMASH - Efficient Sparse Matrix Operation
  • 13a - Memory Controllers
  • 13b - Memory Interference and QoS
  • Discussion Session 1
  • 14 - SIMD Processors and GPUs
  • 15 - Memory Interference and QoS II
  • 16a - Memory Interference and QoS Wrap Up
  • 16b - Emerging Memory Technologies
  • 17 - GPU Programming
  • 19a - Emerging Memory Technologies II
  • 19b - Heterogeneous Computing Systems
  • 20 - Bottleneck Acceleration
  • 21a - Multiprocessing
  • 21b - Memory Ordering(Memory Consistency)
  • 22 - Cache Coherence
  • 23 - Interconnects
  • 24 - Interconnects II
  • Discussion Session 2
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