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  • 1.6 Clock cycle per instruction (CPI)
  • 1.6 Compiler Design - Comparing Code Segment
  • 1.6 Computer performance - CPU time, CPU clock
  • 1.6 Improving performance clock rate v.s cycle counts
  • 1.7 Reducing CPU Power
  • 1.9 SPEC CPU Benchmark – Geometric Mean
  • 1.9 SPEC CPU Benchmark - Introduction
  • 1.10 Amdahl's law
  • 2.2 MIPS assembly language overview
  • 2.5 Translating MIPS Assembly Language into Machine Language
  • 2.7 Compiling a while loop in C
  • 2.8 Compiling a C leaf procedure
  • 2.9 Showing Branch Offset in Machine Language
  • 2.10 Synchronization - Load link & Store conditional instructions
  • 2.11 Linking object files
  • 3.3 Refined Version of the Multiplication Hardware
  • 3.4 A Division Algorithm & Hardware
  • 3.4 An Improved Version of the Division Hardware
  • 3.5 - (1) Binary Floating Point Addition
  • 3.5 - (2) Compiling Floating Point C Procedure with 2D Matrices in to MI
  • 3.5 Accurate Arithmetic – Floating Point
  • 4.3 - Building a Datapath
  • 4.4 - (1) The Datapath in Operation for an R-type Instruction
  • 4.4 - (2) The Datapath in Operation for a LoadStore Instruction
  • 4.4 - (3) The datapath in operation for a branch-on-equation instruction
  • 4.4 - (4) Implementing Jump
  • 4.5 The laundry analogy for pipelining
  • 4.5 - (1) Single Cycle versus Pipelined Performance
  • 4.5 - (2) Forwarding with Two instructions
  • 4.5 - (3) Reordering Code to Avoid Pipeline Stalls
  • 4.5 - (4) Performance of Stall on Branch
  • 4.6 - Control Signals of Pipelined Datapath
  • 4.6 - The Pipelined Datapath for a Load Instruction
  • 4.7 - Conditions of MEM Data Hazard
  • 4.7 - Control signals of MEM Data Hazard
  • 4.7 - Dependence Detection
  • 4.7 - EX Data Hazard
  • 4.7 - Load Use Hazard – Conditions and Stalls
  • 4.8 - Dynamic branch prediction
  • 4.8 - Control Hazards – Performance Impact and Solutions Overview
  • 4.8 - Reducing the delay of branches
  • 4.8 - Scheduling branch delay slot
  • 5.2 - Disk Access Time
  • 5.2 - Sever Computers
  • 5.3 - (1) Bits in a Cache
  • 5.3 - (2) Mapping an Address to a Multiword Cache Block
  • 5.4 - (1) Calculating Cache Performance
  • 5.4 - (2) Calculating Average Memory Access Time
  • 5.4 - (3) Misses and Associativity in Caches
  • 5.4 - (4) Size of Tags versus Set Associativity
  • 5.4 - (5) Performance of Multilevel Caches
  • 5.5 Dependability - MTTF and Availability
  • 5.5 The Hamming Single Error Correction Code (ECC)
  • 6.2 - (1) Speed up Challenge
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