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- 1.6 Clock cycle per instruction (CPI)
- 1.6 Compiler Design - Comparing Code Segment
- 1.6 Computer performance - CPU time, CPU clock
- 1.6 Improving performance clock rate v.s cycle counts
- 1.7 Reducing CPU Power
- 1.9 SPEC CPU Benchmark – Geometric Mean
- 1.9 SPEC CPU Benchmark - Introduction
- 1.10 Amdahl's law
- 2.2 MIPS assembly language overview
- 2.5 Translating MIPS Assembly Language into Machine Language
- 2.7 Compiling a while loop in C
- 2.8 Compiling a C leaf procedure
- 2.9 Showing Branch Offset in Machine Language
- 2.10 Synchronization - Load link & Store conditional instructions
- 2.11 Linking object files
- 3.3 Refined Version of the Multiplication Hardware
- 3.4 A Division Algorithm & Hardware
- 3.4 An Improved Version of the Division Hardware
- 3.5 - (1) Binary Floating Point Addition
- 3.5 - (2) Compiling Floating Point C Procedure with 2D Matrices in to MI
- 3.5 Accurate Arithmetic – Floating Point
- 4.3 - Building a Datapath
- 4.4 - (1) The Datapath in Operation for an R-type Instruction
- 4.4 - (2) The Datapath in Operation for a LoadStore Instruction
- 4.4 - (3) The datapath in operation for a branch-on-equation instruction
- 4.4 - (4) Implementing Jump
- 4.5 The laundry analogy for pipelining
- 4.5 - (1) Single Cycle versus Pipelined Performance
- 4.5 - (2) Forwarding with Two instructions
- 4.5 - (3) Reordering Code to Avoid Pipeline Stalls
- 4.5 - (4) Performance of Stall on Branch
- 4.6 - Control Signals of Pipelined Datapath
- 4.6 - The Pipelined Datapath for a Load Instruction
- 4.7 - Conditions of MEM Data Hazard
- 4.7 - Control signals of MEM Data Hazard
- 4.7 - Dependence Detection
- 4.7 - EX Data Hazard
- 4.7 - Load Use Hazard – Conditions and Stalls
- 4.8 - Dynamic branch prediction
- 4.8 - Control Hazards – Performance Impact and Solutions Overview
- 4.8 - Reducing the delay of branches
- 4.8 - Scheduling branch delay slot
- 5.2 - Disk Access Time
- 5.2 - Sever Computers
- 5.3 - (1) Bits in a Cache
- 5.3 - (2) Mapping an Address to a Multiword Cache Block
- 5.4 - (1) Calculating Cache Performance
- 5.4 - (2) Calculating Average Memory Access Time
- 5.4 - (3) Misses and Associativity in Caches
- 5.4 - (4) Size of Tags versus Set Associativity
- 5.4 - (5) Performance of Multilevel Caches
- 5.5 Dependability - MTTF and Availability
- 5.5 The Hamming Single Error Correction Code (ECC)
- 6.2 - (1) Speed up Challenge
计算机组成原理的相关介绍
本站推荐的这部计算机组成原理视频教程为大家系统地介绍了计算机的基本组成原理和内部工作机制。想学习这方面知识的朋友不妨来外唐网观看、学习一下!
https://www.youtube.com/playlist?list=PLylnxZnYW9LbVL5HnYwo7VLmlkhM7lTey 转自YouTube上台湾云林科技大学上朱宗贤老师的计算机组成原理课程
计算机组成的任务是在指令集系统结构确定分配给硬件系统的功能和概念结构之后,研究各组成部分的内部构造和相互联系,以实现机器指令集的各种功能和特性。这种联系包括各功能部件的内部和相互作用。
计算机组成要解决的问题是在所希望达到的性能和价格下,怎样最佳,最合理地把各个数倍和部件组成成计算机,已实现所确定的ISA。计算机组成设计要确定的方面应包括:(1)数据通路宽度:数据总线上一次并行传送的信息位数。(2)专用部件的设置:是否设置乘除法、浮点运算、字符处理、地址运算等专用部件,设置的数量与机器要达到的速度、价格及专用部件的使用频度等有关。(3)各种操作对部件的共享程度:分时共享使用程度高,虽限制了速度,但价格便宜。设置部件多降低共享程度,因操作并行度提高,可提高速度,但价格也会提高。(4)功能部件的并行度:是用顺序串行,还是用重叠、流水或分布式控制和处理。(5)控制机构的组成方式:用硬联还是微程序控制,是单机处理还是多机或功能分布处理。(6)缓冲和排队技术:部件间如何设置及设置多大容量的缓冲器来协调它们的速度差;用随机、先进先出、先进后出、优先级,还是循环方式来安排事件处理的顺序。(7)预估、预判技术:为优化性能用什么原则预测未来行为。(8)可靠性技术:用什么冗余和容错技术来提高可靠性。
计算机全称:电子计算机,俗称电脑,是一种能够按照程序运行,自动、高速处理海量数据的现代化智能电子设备。由硬件和软件所组成,没有安装任何软件的计算机称为裸机。常见的形式有台式计算机、笔记本计算机、大型计算机等,较先进的计算机有生物计算机、光子计算机、量子计算机等。